1. Field of the Invention
The invention relates to a sensing apparatus; more particularly, the invention relates to a sensing apparatus in which a sensing device includes an amorphous silicon layer and a graphene layer.
2. Description of Related Art
In the existing image sensing array, each sensing pixel usually includes one thin film transistor (TFT) and one PIN diode. The TFT serves as a switch device performing a reading function, and the PIN diode acts as a sensing device which converts optical energy into electronic signals.
Generally, in order for the image sensing array to achieve remarkable quantum efficiency (QE), i.e., incident photon-to-electron conversion efficiency (IPCE), a PIN layer with sufficient thickness (about 1.0 μm to 1.5 μm) is often required to be deposited, and thus the protection layer that protects the PIN layer is also required to have the sufficient thickness. As a result, the conventional image sensing array not only has the large thickness but also requires significant time spent on depositing the PIN layer and high manufacturing costs. Besides, the conventional image sensing array can be completely formed by performing eleven photolithography and etching processes (PEPs) in most cases, which further complicates the manufacturing process. Hence, how to reduce the number of times of performing the PEPs for manufacturing the image sensing array and reduce the complexity of the overall manufacturing process has become one of the important research and development tasks.